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Best choice for large farms for Verilog simulation |
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Supports the entire Verilog language, user defined primitives,
specify blocks, system tasks and functions, PLI 1.0, VCD
and SDF. |
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Supports compiled, interpreted, and any mixture of compiled
and interpreted simulation |
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First mixed event and cycle driven simulator for Verilog |
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Smart partitioner analyzes the design and decides which
areas can be simulated by the Enhanced Cycle Simulation
(ECS) kernel |
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Able to handle modules with path delays as well as some
RTL-level modules, and fully supports Xs and Zs as well
as the entire range of Verilog strengths. |
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Supports all popular waveform display tools including
Veritools' Undertow, Cadence's Signalscan |
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Rated the fastest Verilog simulator In the DA Solution
Limited `96 benchmark |
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FinSim was rated the fastest PC-based Verilog simulator
in the ASIC & EDA benchmark. |
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Super-FinSim runs on all popular platforms including
Sun Solaris, HP UX, DEC Unix, DEC NT and PCs running Windows
NT/2000, Windows 95/98/ME and Linux |
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Add-on components include code coverage and Verilog
Analyzer |