VirtualScan
Advanced Scan Compression, Scan Synthesis, Scan Insertion, ATPG, Fault Coverage, and Test Generation
|
|
Xtreme Compression Scan Technology
VirtualScan™ combats the increasing test data and test cycle volume.
With VirtualScan™ an extremely large number of short scan chains
within the SOC can be virtually accessed from outside the chip with a
limited number of pins assigned as scan pins. Inside the chip, SynTest's
new patent-pending circuitry is used to broadcast each external scan-input
chain to a user-selectable number of internal scan chains and at the other
end, compact them into the original number of external scan chains. An
evaluation on a 2-million gate design using VirtualScan™ showed a
22x reduction in test time. Further, the static and dynamic compaction
capabilities of SynTest's powerful ATPG tool help reduce pattern sizes,
leading to overall reduction in test costs.
Features:
 |
Patent-pending virtual scan technology for broadcasting external scan chains to a user-selectable number of shorter internal scan chains and compacting them back into original number of external scan chains |
|
Automatically inserts broadcaster and compactor circuitry |
|
Outputs complete virtual scan netlist |
|
Includes tools for scan insertion and synthesis |
|
Uses an enhanced virtual scan ATPG |
|
Static and dynamic compaction of ATPG patterns |
|
Advanced multiple clock domain handling using proprietary multiple-capture-per-cycle scheme |
|
Can be used with scan chains inserted using third party tools |
|
Fully compatible with SynTest's existing DFT tools as well as TurboDebug-SOC/Scan and TurboDiagnosis-Scan for scan debug, diagnosis and failure analysis |
More Information:
|
VirtualScan Datasheet (PDF) |
Related Products
|
DFT-PRO Plus |
|
TurboBist-Logic |
|
TurboDebug - SoC and board debug |
|
TurboFault |