TurboScan -- Advanced Scan Synthesis, Scan Insertion, ATPG, Fault Coverage, and Test Generation

TurboScan
Advanced Scan Synthesis, Scan Insertion, ATPG, Fault Coverage, and Test Generation

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Highlights

Repairs violation automatically

Compaction up to 50%

Full and partial scan

Advanced Scan Technology
TurboScan™ is an advanced full-scan and partial-scan test suite. It includes a Scan Synthesizer and an Automatic Test Pattern Generator (ATPG). TurboScan automatically repairs testability violations to make your design highly testable. The ATPG engine uses advanced search and compaction algorithms to achieve very high fault coverage and produce up to 50% smaller test pattern size. TurboScan is designed to reduce product defect level and save test costs.

Features:

Scan Selection and Synthesis - Automatic scan selection based on your clock domain circuitry.

Scan Extraction and Debug - Built-in scan extraction utility recognizes blocks with pre-synthesized scan chains and incorporates these existing scan chains into the rest of the design.

Sequential and Combinational ATPG - Generates highly optimized test sets for full-scan, partial-scan, and non-scan designs. TurboScan algorithms work on asynchronous sequential circuits containing gated clocks, RAMs, ROMs, tri-state gates, asynchronous set/reset, and unidirectional MOS transistors. For full-scan designs, sequential ATPG can be used after combinational ATPG to further improve fault coverage.

Very High Fault Coverage - Handles complex design structures (such as bi-directional pins, transparent latches, bus contention resolution, rippled sets/resets, bus keepers, and multiple phase clocks) for DFT to increase fault coverage. TurboScan supports write and read of memories to allow surrounding logic to be detected.

Advanced ATPG search engine - Uses a 32-value system (compared to the traditional 4-value system) to reduce the search space during ATPG. This improves the speed of the ATPG process and further increases the circuit's fault coverage.

Extremely Compacted Test Sets - Utilizing dynamic and static vector compaction to reduce test sets. This reduces the amount of tester memory needed and shortens the tester time required, saving your overall test costs.

Transition and Path-Delay Capability - Supports transition faults to detect difficult faults such as those at the tri-state enable pins. TurboScan's timing option generates test patterns for critical path delay faults and eliminates false paths from timing analysis.

Test Generation Modes Supported:
- Full-scan, Partial-scan, or Non-Scan
- Fault Model: Stuck-at, Iddq, Transition, and Path Delay fault
- Toggle Transition and Toggle State Coverage

More Information:

TurboScan Datasheet (PDF)