TurboFault
Fast, Concurrent Fault Simulator with SDF Timing Support
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High Performance Fault Simulation
TurboFault™ combines high performance, versatility and accuracy.
It is highly competitive with hardware accelerators for classical test
fault grading. It supports synchronous and asynchronous designs at the
gate level, including tri-state gates, latches, flip-flops, single and
multi-port RAMs, complex bus resolution functions, and User Defined Primitives
(UDPs). TurboFault reads Verilog gate-level netlists, and will also read
Standard Delay Format (SDF) timing files.
Features:
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High Performance Fault Simulation - The fastest concurrent fault simulator based on the latest advances in cycle-based simulation technology. It simulates even faster than existing expensive hardware-accelerated fault simulators. No other fault simulator, hardware or software, matches the performance of TurboFault™. | ||||||||||||
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Advanced Cached-Concurrent™ Algorithm - Optimized for modern computer hardware that maximizes the power of today's workstations. Cached-Concurrent™ algorithm eliminates needless operations and with new Fast Queue™ technology combines the best of unit delay and cycle-based capabilities. |
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SDF Timing - Supports single timing delay for simulation accuracy and flexibility, without sacrificing speed. | ||||||||||||
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Efficient Memory Management - Combines very efficient memory management with special fault handling capability resulting in low memory consumption. TurboFault™ provides special handling for Oscillating and Hyper-active faults. | ||||||||||||
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Sample TurboFault™ Single Workstation Performance:
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Test Vectors - TurboFault accepts Verilog VCD, WGL, TDL, and SynTest ATPG patterns as input stimuli. | ||||||||||||
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Multi-Pass and Incremental Simulation - TurboFault™ determines the optimal configuration and can partition the faults into separate groups and submit simulation tasks in multiple passes for each group. This automatic partitioning capability reduces the number of faults per pass and thus reduces paging. The results from different groups are then automatically merged in the final report. TurboFault™ provides an easy way to accumulate fault grading results from different fault simulation sessions. | ||||||||||||
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User Definable Fault Detection Criteria - Users define the criteria for a fault in order for it to be declared as detected. This gives the simulator the highest flexibility to emulate many test environments and Automated Test Equipment. | ||||||||||||
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Fault Tracing Capability - Allows users to compare the circuit activities between faulty and normal chips. This diagnostic feature can speed up tuning test vectors, isolating faulty circuits and debugging failed parts. | ||||||||||||
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Crash Recovery Capability - The crash recovery function allows recovery of the simulation data and protects results from any environmental adversities, such as network glitches and power outages. | ||||||||||||
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User Interface & Library Modeling - TurboFault™ accepts gate-level cell descriptions and User Defined Primitives (UDPs). SynTest also provides a cell library builder to build gate-level models. TurboFault™ memory modeling provides basic memory building blocks for handling ROMs, and single and multi-port RAMs, either synchronous or asynchronous. | ||||||||||||
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Reporting - TurboFault™ produces concise, detailed reports on fault coverage and fault classifications. In addition, undetected faults can be passed directly to TurboScan for additional processing. TurboFault™ reports faults as Hyperactive, Oscillatory, Hard Detect, Probably Detected, Potentially Detected, Undetected, or Uncompleted. |
More Information:
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TurboFault Datasheet (PDF) |
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