eCheck -- RTL-to-Gate and Gate-to-Gate Equivalency Checking

Prover eCheck
RTL-to-Gate and Gate-to-Gate Equivalency Checking

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Highlights

Fast Performance

Easy-to-Use

#1 in Price/Performance!

Equivalence Checking

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Prover eCheck is an equivalence checking product that dramatically reduces the time needed to verify the many design transformations that are performed in ASIC, IC, SoC and FPGA development flows. Equivalence checking is the only way to exhaustively verify that a change to a design did not alter its functionality. Prover eCheck compares two revisions of the same design, verifying that they are functionally equivalent, or pinpointing any bugs present. Its static formal verification approach is significantly faster than simulation, does not require any test vectors and gives 100% coverage.

Features:

Intuitive graphical user interface (GUI) with a corresponding batch command tool

Automatic Compare Point Mapping. Supports one-hot encodings and automatically maps all state points by utilizing name information, state point functional analysis and state point structural information.

High Capacity, Fast Runtimes. Handles multi-million gate design capacity and consumes only 500MB per million gates enabling the user to run large designs without partitioning.

Supports all common flows, all common HDLs (including libraries) and runs on Windows (NT/2000IXP), Linux and Solaris.

Verified interoperability with the most common synthesis, test logic, timing and P&R tools ensuring wide and robust applicability.

Efficient Debug Capabilities. Integrated debugging capabilities pre-processes all failing compare points and optimizes for easiest error detection possible.

More Information:

Prover eCheck Datasheet (PDF)