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TurboCheck
RTL and Gate-Level Testability Analysis
RTL and Gate-Level Testability Analysis
TurboCheck™ is a Testability Analyzer and Test Assistant
for both RTL and gate-level digital designs. TurboCheck analyzes
the testability of sequential circuits and assists the designer
in selecting test solutions that are most likely to improve
the circuit's final fault coverage. TurboCheck operates on
non-scan, partial-scan, or full-scan circuits. Because it
is a static tool operating on the topology of the circuit,
no vectors are needed for the analysis.
Features:
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TurboCheck-RTL - Identifies testability problems at
the earliest stage of the design cycle - right after RTL
coding. With TurboCheck-RTL, up to 80% of the testability
rule violations are detected sooner during RTL coding
before synthesis. |
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TurboCheck-Gate - Used after the design is synthesized
into gates. Since the RTL design has been checked by
TurboCheck-RTL before synthesis, TurboCheck-Gate can
perform a structural-level check once or twice on the
final design to further identify and zero-in on the
final testability violations that cannot be detected
at RTL coding.
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Provides Immediate Feedback - Potential design and testability
problems are detected during the design phase of the circuit,
allowing changes to be made early in the design process.
This flow minimizes the impact of testability considerations
on other important constraints of the design. Since TurboCheck-RTL
checks your RTL codes, it does not depend on the type
of technology libraries used in the design. Therefore,
designers will get immediate benefits from TurboCheck-RTL
without having to learn a new design flow. |
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Computes Controllability and Observability Values -
Computes values according to the structure of the design.
These testability values are used to identify test problems
that could possibly affect the fault coverage of the design.
TurboCheck reports the nodes that are either uncontrollable
or unobservable. This allows a designer to quickly isolate
and review potential problem areas. |
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Highlights Potential Circuit Testability Issues - Beyond
just computing testability values, TurboCheck identifies
test problems such as combinational feedback loops,
generated clocks, gated clocks, floating buses, and
many other logical design guidelines for testable circuit
design. These reports direct the designer to the precise
location in the design where the problem occurs, enabling
quick scan of the design for test issues.
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Selects Scan and Test Points - With TurboCheck-Gate
as Test Assistant, you select manual or automatic insertion
of test points. With automatic scan selection, TurboCheck-Gate
will recommend a near-optimal set of test points for test
control, test access, or both. When scan selection is
done manually, TurboCheck-Gate allows selection of test
points using any external scan selection algorithm, and
analyzes the effect of the selection on the testability
of the circuit. By manually selecting or excluding scan
points, timing-critical circuitry can be excluded from
the scan chain to minimize the impact of scan on design
performance. |
Testability Problems Identified:
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Floating Nets and Ports |
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Combinational Feedback Loops |
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Uncontrollable or Unobservable Nodes |
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Potential Bus Contention |
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Floating Busses |
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Combinational Gated Clocks |
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Sequentially Generated/Gated Clocks |
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Sequentially Generated/Gated Asynchronous Set/Reset |
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Transparent Latches |
Supported Input Formats:
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TurboCheck-RTL: Synthesizable Verilog RTL |
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TurboCheck-Gate: Structural-Level Verilog, VHDL |
Platforms:
More Information:
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