TurboBSD Boundary Scan Synthesis, BSDL Creation, Pattern Generation Next Step Download Software Request for Quotation Highlights Best-in-Class Technology Compliance Checking Synthesis & Pattern Generation #1 in Price/Performance! Boundary Scan Synthesis, BSDL Creation, Pattern Generation TurboBSD™ is SynTest high-performance Boundary Scan Designer. It is 100% compliant to the IEEE 1149.1 Boundary Scan Standard. TurboBSD performs Boundary Scan logic synthesis, creates BSDL (Boundary Scan Description Language) file, and generates Boundary Scan test patterns. All these tasks are fully automated by the tool, making boundary scan design a straightforward process. Features: Boundary Scan Synthesis - Outputs synthesizable Verilog or VHDL RTL codes. The RTL codes can be customized for your applications and later synthesized using your own technology libraries. Alternatively, TurboBSD can directly output Verilog or VHDL cell-level logic. TurboBSD also supports custom ID code and private instructions. As part of the Boundary Scan Synthesis process, TurboBSD will buffer the controlling signals (shift_dr, clock_dr, etc.) from the TAP controller to drive boundary scan cells BSDL File Generation - Extracts the boundary scan chain information from the circuit and creates BSDL file from the boundary scan descriptions provided by your IC vendor. Alternatively, TurboBSD includes a handy on-line form utility for designer to input the BSDL information directly. TurboBSD will then create the BSDL file for your design Automatic Test Pattern Generation - Automatically generates implementation and fault model independent functional test sets. These patterns are used to verify the Boundary Scan logic integrity, including public instructions such as BYPASS, EXTEST, INTEST, and private instructions such as BIST. The patterns are modularized for easy debugging. TurboBSD also generates parametric tests (e.g., VOH, VOL, VIH, VIL). For designs that incorporate built-in self-test (BIST), TurboBSD generates test patterns to control BIST operations using the test information specified in TI Serial Vector Format (SVF). The test information in SVF will allow the TAP Controller to start and stop BIST operations Flexible Tool Architecture - TurboBSD is designed with flexibility in mind. The three main functions of the tool (boundary scan synthesis, BSDL file creation, and test pattern generation) are separated into three distinct processes within the tool. This allows the designer to use other EDA tools for boundary scan synthesis, and use SynTest's TurboBSD for BSDL file creation and test pattern generation Flexible Input and Output Formats - TurboBSD is easily integrated into your design and test environment. It reads Verilog, VHDL, EDIF and TDL netlists. TurboBSD can output either RTL or cell-level netlist. The output netlist can be in Verilog or VHDL format. The RTL netlist is useful for synthesizing into your own technology library cells. For test patterns generation, TurboBSD can output Verilog or VHDL testbench. It can also output HP VCL format Fully IEEE 1149.1 Boundary Scan Standard Compliant Boundary Scan Synthesis for TAP Controller, ID Code, and Public and Private Instructions RTL or Gate Level Netlist Generation On-Line Form Boundary Scan Description Entry Automatic BSDL Generation to Minimize Errors Automatic Boundary Scan Verification Test Generation to Verify Scan Chain Integrity Including: Functional Tests for Public Instructions such as BYPASS, EXTEST, INTEST, CLAMP, HIGHZ, and SAMPLE/PRELOAD Functional Tests for Private Instructions such as BIST by using TI SVF syntax Parametric Tests for VOH, VOL, VIH, VIL, etc. Input Format: Verilog, VHDL, EDIF, TDL Netlists, Boundary Scan Description File Output Format: Verilog, VHDL Netlists, and Testbench in Verilog, VHDL, HP VCL Platforms: Sun Solaris HP-UX Linux More Information: TurboBSD Datasheet (PDF) Related Products VirtualScan - xtreme compression TurboDebug - SoC and board debug TurboCheck - testability analysis