TurboBist-Logic At Speed Logic Testing Next Step Download Software Request for Quotation Highlights Best-in-Class Technology Ideal for High Reliability Applications At-speed Fault Dectection #1 in Price/Performance! "At-Speed" Logic Test TurboBIST-Logic utilizes the powerful Pseudo-Random Pattern Generation (PRPG) technique with scan chains and a Multiple-Input Signature Register (MISR). Design architecture specific PRPG, MISR & Controller are synthesized at Verilog or VHDL RTL. SynTest's own scan-chain related comprehensive tool set for selection, repair, reorder & debug makes the implementation a breeze. Unique Multiple-capture-per-cycle schemes aid in improved fault coverage, especially for extremely large and complex designs with multiple-frequency clock domains. It allows Test Point insertion in the design for increased testability and, thus, fault coverage. TurboBIST-Logic conducts fault coverage analysis with a super-fast, cycle-based fault simulator. To increase fault coverage and limit iterations and overhead related to Test Point insertion, TurboBIST-Logic works in tandem with SynTest's proprietary sequential ATPG technology that supports full-scan and partial-scan. TurboBIST-Logic works with SynTest boundary-scan (TurboBSD) and memory BIST (TurboBIST-Memory) products to implement SoC level testability schemes, enabling comprehensive board/system level tests. Benefits: At-speed testing for multiple-frequency clock domains Concurrent testing of all clock domains Multiple-capture per cycle aids in improved fault coverage Test point insertion Support for multiple seed strategy Tightly integrated with SynTest's TurboScan-ATPG to achieve high fault coverage and reduce test time Equipped with super-fast cycle-based fault simulation Automatic repair of most BIST violations Platforms: Sun Solaris HP-UX Linux More Information: TurboBist-Logic Datasheet (PDF) Related Products TurboBist-Memory VirtualScan - xtreme compression TurboDebug - SoC and board debug